I. Introduction
In recent years, there has been an increase in concerns surrounding hardware trust and security due to the globalization of chip fabrication [1]. Most foundries are located outside of the United States. There are various places in the supply chain where chip designs can be reverse engineered, duplicated, counterfeited, stolen, and otherwise compromised. Design obfuscation has become a necessary countermeasure to this sort of malicious activity. Design obfuscation can prevent reverse engineering in two ways. First, it can prevent the malicious agent from learning and reproducing the chip’s design and function when they have obtained a physical copy of the chip. Second, it can prevent an untrusted foundry from ascertaining the function and proper operation of the chip even when they have the actual chip design. A common form of design obfuscation is via insertion of switchbox (SB). SBs can be programmed by the designer after the fabrication in untrusted foundry and allow for the routing of signals within a circuit to a desired location known to the designer and end user, but not to an untrusted foundry. A common way that this is implemented is with pass transistors with SRAM memory [2][6]. However, SRAMs are known to suffer from issues such as scalability, increased power consumption, and are expensive to fabricate [8]. Additionally, these are volatile-memory devices which means reconfiguration bits needs to be stored in an on-chip non-volatile memory in case of power-loss. Resistive Random-Access Memory (RRAM) devices have emerged as a popular option for replacing or augmenting SRAM-based SBs in hardware [4][6][7]. RRAM devices are scalable, reprogrammable, and non-volatile, making them an attractive option since they do not need to be reprogrammed every time power is cycled. RRAM devices and associated programming circuitry have an application in SBs designs for FPGA-based architectures. However, prior research has explored RRAMs with CMOS-Field Effect Transistors (FETs) where CMOS-FETs were fabricated in Front End of Line (FEOL) that consumes the expensive area on the chip in FEOL [2][6]. Our approach uses RRAM devices in conjunction with thin film transistors (TFTs) that can be completely fabricated into Back-End-of-Line (BEOL). This approach will allow for split-manufacturing with ease or additive manufacturing where RRAM-TFT-based SBs can be integrated on pre-fabricated CMOS dies at low-volumes in trusted foundries. Finally, we demonstrate application of RRAM-TFT based SBs for asynchronous reprogrammable gates to provide a scalable approach to achieving secure asynchronous FPGA designs.