Minimizing Signal-Dependent Residue in CT Pipelined ADCs

A continuous-time (CT) pipelined analog-to-digital converter (ADC) profits mostly from a large inter-stage gain (ISG). This gain is constrained by two major factors: coarse stage quantization noise (QN) and signal leakage. With both being as low as possible, the ISG can be increased while overloading of the fine stage is prevented, leading to the best possible performance. The coarse stage’s QN can only be reduced by increasing its resolution. The signal leakage on the other hand can be adjusted in the analog domain by selecting a suitable all-pass filter (APF) topology and optimizing it. This paper presents several methods to specify the core parameter of the APF, i.e. its nominal delay time T
d
. Furthermore, the use of an extra low-pass filter (LPF) is investigated and tradeoffs concerning signal leakage, transfer function error and robustness to process deviations are shown.