High-Precision Priority Encoder Based Integer Division Algorithm

In the past years, the demand for high-precision arithmetic has significantly increased, which raised the need for devices that can handle high-precision computations. Therefore, in this paper, we propose a hardware for high-precision division. The proposed hardware is implemented for 1024 bits, and it can be easily extended to larger bits. The hardware performs division on integer numbers represented in sign and magnitude, and produces quotient and remainder. A priority encoder is used to improve the convergence rate, and to make the dividend and divisor lengths not required as inputs. To reduce complexity, most of the components were implemented in two levels. We provide an upper limit and a closed-form expression for the convergence rate. We synthesized the hardware on a Field-Programmable Gate Array (FPGA) device. We simulated the hardware at the bit level in Matlab using Monte Carlo simulations. We also simulated the hardware in ModelSim. Compared to the existing approaches, the results show that for 64-bit division, our hardware reduces the number of LUTs and slices by 18.4% and 67.5%, respectively, and improves delay by 50.3%. As for 256-bit division, our hardware reduces the number of slices by 60.7% and improves delay by 33.25%, however, it increases the number of LUTs by 11.32%.