Evaluating the Performance, Energy and Area Tradeoffs of ATHENA in Superscalar Processors

Coarse-Grained Reconfigurable architectures (CGRA) have been widely used as accelerator, providing energy saving and performance improvements while also offers flexibility to meet different applications requirements. Despite the aforementioned advantages, CGRAs usually consist of many processing elements, which implies area overhead that can be prohibitive to its integration in system with hard area constraint, such as embedded system and mobile devices. To cope with that, this work evaluates a CGRA for systems with hard area constraint called ATHENA (A Thin rEcoNfigurable Architecture). The thinness concept consists of a CGRA that uses considerably less processing elements than the CGRAs found in the literature. ATHENA is attached to a superescalar processor and is dynamically mapped. A design space exploration on ATHENA and the superescalar processor is carried out to evaluate the different area, energy and performance tradeoffs that these solutions can deliver. The results shows that, even using fewer processing elements, ATHENA was able to speed up to 2.43x while saving up to 32% of energy. When compared with other dynamically mapped CGRAs of the state of the art, ATHENA is up to 4x smaller and provides competitive performance.