Modeling of Reconfigurable ΣΔ Modulator for Multi-standard Wireless Receivers in Verilog-A

This paper presents the modeling and design of a reconfigurable
$\Sigma\Delta$
modulator in Verilog-A language for applications in multi-standard wireless receivers. Main building blocks are implemented separately and its development detailed. Results presented are from simulations in SPECTRE circuit simulator in Cadence Virtuoso Analog Design Environment using Verilog-A models of main sub-circuits. The modulator achieves SNR values of 78.7 dB for GSM (EDGE) operation (200 kHz bandwidth), 79.9 dB for Bluetooth operation (500 kHz bandwidth) and 55.3 dB for UMTS (W-CDMA) operation (2 MHz bandwidth).