High Efficiency & Low Area DC-DC Buck Converter with the Digital Feedback Loop for the Wireless Applications

In this Paper, a high efficiency and low area dc-dc buck converter with the digital feedback loop is proposed for wireless device. The digital feedback loop is consisted of two-step digital pulse width modulation (DPWM) and low power self-tracking zero current detector (ST-ZCD). To implement a high-efficiency dc-dc converter, a hybrid DPWM core is proposed with high linearity and low power consumption. To reduce the output voltage ripple within 20mV, an adaptive window analog-to-digital converter is proposed. To minimize the reverse current, a dead time generator is implemented with the proposed ST-ZCD. The circuit is designed with a Samsung 28nm CMOS process that produces an output voltage of 1.8V using a standard supply voltage of 3.3V.