Stability Investigation of PLL-Based Grid Synchronization

This contribution investigates the grid synchronization procedure of grid-side inverters, i.e. the correct determination of the grid voltage frequency. A phase-locked loop (PLL) can be seen as the standard method for grid synchronization. Due to the grid impedance, the grid voltage cannot be measured directly and the measured voltage is a superposition of the grid voltage and the inverter voltage. Therefore it is possible that the PLL loses synchronism with the grid and tracks the inverter voltage instead. In stiff grid scenarios this effect may be neglected, but in the case of a weak grid, a failure of the PLL to synchronize with the grid is likely. Since the grid synchronization procedure depends not only on the grid impedance but also on the filter impedance of the inverter as well as on the point of operation, a comprehensive analysis under what circumstances the loss of synchronism occurs is needed. In this paper the described scenario is studied and a necessary condition for a successful grid synchronization in the stationary case is derived. The condition depends on all parameters of the system model and is verified in numerical simulations.