Patterning Techniques for Copper Electoplated Metallization of Silicon Heterojunction Cells

The CSEM reference process comprises a sputtered seed layer and patterning by hotmelt-inkjet printing. As alternative patterning technique the formation of seed-grid lines by screen-printing of silver or copper paste is investigated. The seed-grid is subsequently reinforced by electrodeposition of copper to improve the conductivity. As plating mask either an inorganic dielectric layer or a self-assembled monolayer of organic molecules is used. The resistance of grid lines printed with silver or copper paste and the resulting cell efficiency before and after copper plating are compared.