Minimized Region of Path-search Algorithm for ASIP-based Connection Allocator in NoCs

A centralized resource allocation technique in Network-on-Chips (NoCs) has proven to be crucial to ensure service guarantee in real-time applications. The recently introduced Application Specific Instruction Processor (ASIP) approach, which combines the flexibility of software with the speed of hardware solutions, has achieved a remarkable reduction in path search time at moderate hardware costs increase comparable to pure software solutions. However, in large networks, the ASIP approach exhibits performance losses compared to the hardware solution, which is a problem for applications that optimize allocation dynamically according to the workload profile. To overcome this scalability problem, we propose a new path search algorithm and a flexible, efficient ASIP architecture. Instead of a global search region, the path search is performed within a reduced path search region, which moves along the search trajectory from source to target during the search. This eliminates reasonably the calculations in the path search process, while performance is only slightly reduced compared to global search techniques. The simulation results clearly show the scalability of our approach, where at similar hardware costs, the path search in the 16×16 2D mesh was reduced by a factor of ten compared to the recently proposed approach for the adaptive search region.