Research on Dead Time Compensation of Parallel Multilevel Topology Structure

Inverter dead time compensation algorithm has always been a hot spot in the field of motor control. Parallel multi-level topology inverters can achieve the goals of high switching frequency and high power through the parallel connection of power devices, and are widely used in motor simulators and power systems. This article first quantifies the cause of the output waveform distortion of the three-phase voltage inverter, and derives the error voltage formula due to the non-ideal characteristics of the inverter under the parallel multi-level structure based on this. Finally, based on the determined parallel multi-level topology, an accurate dead-zone compensation scheme is proposed. Simulations verify the effectiveness of the dead-zone compensation strategy proposed in this paper to suppress the output voltage and current harmonics.