Configurable Precision IEEE 754–2019 Floating-Point Square Root IP using CrossLink-NxFpga

With the expiration of IEEE 754–2008 last 2018, a new standard IEEE 754–2019 has been made with some revisions from the previous standard specifically on the precision formats in which the square root calculations for digital signal processing conforms to this standard. This paper presents a new floating-point square root IP which allows configuration of different precision formats of IEEE 754–2019 - Half, Single, Single Extended, and Double Precisions - and undergoes full FPGA flow. The IP configurability of this study offers wider solutions from low-area applications to high-end processing. This paper uses modified non-restoring algorithm and employs pipelining to achieve a high-speed requirement of greater than 100 MHz for all formats. Synthesis and verification assessments are done in Lattice CrossLink-NX (LIFCL-40) FPGA using Lattice Radiant Software 2.1.