Suppressing Ambipolar Conduction in Silicon DGTFET: Comparing Gate-to-Drain Overlapping/ Underlapping Structure

Silicon double gate tunneling field effect transistors, DGTFETs are suitable candidates for integration with current CMOS technology. Although their high ON/OFF current ratio and low subthreshold swing, they suffer from unwanted ambipolar conduction. In this work, a comparison of three TFET device structures is reported utilizing a TCAD simulator to determine the most suitable candidate that gives minimum ambipolarity and maximum cut off frequency. Insertion of low-k spacer above the drain region, using asymmetric gate electrode and using gate underlap with a lowk spacer below are compared in above terms. The merits of each design are shown and explained