Versatile Hardware Architecture of a Support Platform for Spatial Image Processing Accelerators using Xilinx SoCs

In this paper, a novel hardware architecture of a support platform for spatial image process accelerators using Xilinx SoCs is presented. The proposed architecture supports any spatial image processing accelerator that maintains a simple handshaking protocol regardless of the latency of the accelerator. The design of the support platform allows rapid development of spatial image processing accelerators by isolating the complex task of managing the data transfers back and forth from the main memory. Multiple instances of the support platform were instantiated using two different edge detection accelerators at a core clock rate of 105 MHz for test purposes. The system was processing 1920x1080 pixel frames at a rate of 205 frames per second. The importance of this research is to provide a scalable platform for high-performance video image processing applications like in medical robotics.