Improvement of Count Rate for Pixelated CdZnTe Detector Array

For traditional analog ASIC, it needs a long time to serially read out the analog signals of all channels. In this study, the variable sampling time is used to reduce the readout time for sparse triggered channels, and only the analog signals of the triggered channels are sampled for a long time. In order to avoid the false triggers from the cathode signals with poor SNR, only the ASIC's anode channels are used to generate the trigger signals, and the cathode waveforms are sampled by an external high-speed ADC. This system contains a 2×2 detector array, and the readout electronics working in the independent mode can significantly improve the count rate.