Advances in Dry Etch Processing for High-Density Vertical Interconnects in Fan-Out Panel-Level Packaging and IC Substrates

Within the advanced packaging technologies there is an increasing demand for very high I/O count solutions to fulfill requirements of high performance computing applications like big data analysis. Thus, the density of lateral and vertical interconnects is being pushed to its limits to achieve a minimum delay in communication between chips or chiplets from different technology nodes. Here we focus on dry etch technology as an approach to overcome the difficulties of currently used processes for the formation of vertical interconnects (vias) in organic buildup films. Nowadays, laser drilling into the organic dielectric is the state-of-the-art technology to prepare vertical interconnects between the Cu layers. However, drawbacks like sequential processing, limited control of sidewall smoothness or registration accuracy become extremely challenging when millions of sub-vias have to be realized on 600 mm2 panels. One alternative technique to address the need of forming steep microstructures in various materials is deep reactive-ion etching (DRIE). In this paper we analyze how DRIE could be applied for via formation in silica-filled organic dielectric build-up films. Our approach included a metallic hard mask for material-selective etching and for generating various via diameters. For our experiments, a dual frequency capacitive coupled plasma (CCP) tool was used. The plasma etch module was designed for panel-level substrates up to size and was integrated into a high volume manufacturing system. We investigated the influence of different gas mixtures, power settings on etch rate, selectivity (e.g. on silica and organic), directionality, uniformity and homogeneity. The overall compatibility and implications of the dry etching approach for the semi-additive process and redistribution layer formation have been discussed.