3D Finite Element Simulation Study of Chip Stacking Structure Considering Different Numbers of Stacked Dies and the Effects of Underfill and Intermetallic Compound Layer of Micro-joints

High Bandwidth Memory (HBM) is a representative product of three-dimensional integrated circuit (3D IC) integration and it has become a standard scheme for dynamic random access memory (DRAM), which has been enabled with 16-layer stacks in production and is heading for more stacking layers. In this study, the finite element models with different numbers (N=2, 4, 8, 12 and 16) of layers of stacked DRAM chips are constructed and used to characterize distributions of von Mises stress and nonlinear strain energy density in micro-joints consisting of solder cap and Cu pillar. The influences of underfill (UF) and intermetallic compound (IMC) on micro-joints are analyzed for the stacking structure with a critical number of layers. Simulation results manifest that the solder in N=8 model suffers larger stress and higher strain energy density than other models. Stacking more DRAMs with increasing N from 12 to 16 by reducing the thickness of chips and UF can result in an obvious increase of the stress in Cu pillar. Interestingly and arguably, the presence of UF seems to show a side-effect on the thermomechanical reliability of micro-joints, and IMC layer leads to the increase of stress in Cu pillar.