Pre-bond Qualification of Through-Silicon Via for the Application of 3-D Chip Stacking

In this paper, the fabrication of the through-silicon via (TSV) is introduced and characterized. Pre-bond structural analysis and electrical tests were performed and analyzed to examine the robustness of the fabrication process and the structural integrity of the TSVs. It is shown that the TSVs are robust even after given stress. The influence of the presence of TSVs on nearby metal-oxide-semiconductor field-effect transistor (MOSFET) devices and metal interconnects is also characterized by means of electrical tests. The results show that the fabricated TSV is robust and that the presence of TSV does not pose significant impact on the performance of MOSFET as long as they are sufficiently distanced from each other.