Fine RDL patterning technology for heterogeneous packages in fan-out panel level packaging

Since InFO WLP (Integrated Fan-out wafer level package) technology was successfully launched on the packaging field in 2016, the interest in fan-out package technology has increased significantly due to small footprint, enhanced speed gain and power dissipation. And then, fan-out panel-level packaging (FOPLP) has been proposed in order to increase the throughput. Panel level packaging(PLP) shifts packaging format from wafer to large panels because of potential cost reduction, high volume manufacturing (HVM) efficiency, and flexibility for applications such as chip first and chip last approaches. This attracts players with many different business models, including outsourced semiconductor assembly and test (OSAT), integrated device manufacturers (IDMs), foundries, substrate manufacturers and FPD players. The capability of fine RDL patterning technology is crucial to integrate several active and passive components for next-generation packaging technology. We demonstrated the capability of the formation of 2 um Cu trace using semi-additive process without additional investment of equipment to satisfy these requirements. In addition, we focused on the influence of seed metal layer for via coverage and the optimization of wet etch amount to achieve the design rule of line/space (L/S) 2/2 and reduce the degree of undercut.