Multi-Terminal Low-ESL 3D Silicon Capacitors as Enabler for Optimized and Flat PDN Design

Both in Mobile and High-performance Computing (HPC) applications, efficient power supply of the processors was and is still being a big challenge for designers. Indeed, for these applications the power consumption is increasing while the power supply voltage is decreasing in alignment with the latest technological nodes (7nm, 5nm, 3nm…). Thus, lowering and flattening the Power Distribution Network (PDN) impedance is more than ever important to mitigate the voltage fluctuation, the resonance and anti-resonance peaks caused by the PDN's components. Such optimization is done by tuning the features of the different decoupling capacitors used along the power path from the power supply down to the processor. So, by increasing the capacitance, lowering the Equivalent Series Inductance (ESL) and adjusting the Equivalent Series Resistance (ESR) of the different decoupling capacitors, one can manage to have a very low and flat PDN impedance. An overview of the existing 3D Silicon Capacitors (Si-Cap) is presented. Comparison with classical decoupling components will be done and different assembly configurations are discussed (Die side, Embedded, Land side). These components bring unprecedented design flexibility and demonstrated significant improvements by reducing the voltage drop and enabling an efficient power noise reduction.