Investigation of Low Stress and Low Temperature SiN and SiCN PVD Films for Advanced Packaging Applications

Hybrid bonding or surface activated bonding is becoming a very attractive technology to manufacture higher performance CMOS by addressing pitch scaling difficulties of solder interconnects. One of the major challenges for dielectric bonding is to decrease the process temperature to be compatible with CMOS processing. Many investigations have demonstrated low bonding temperatures (annealing temperatures below 250°C) with either SiCN or SiN. In this paper, we focus on the dielectric layer deposition process. Both low temperature physical vapor deposition (PVD) of SiN and SiCN are investigated side by side. Film stress as function of film thickness is characterized to understand its potential impact on wafer warpage. Reliability of low temperature SiN film is tested on both inorganic and organic surfaces so it can be leveraged in a wide set of wafer level packaging applications.