Synthesis and Implementation of Reconfigurable Reversible Generalized Fredkin Gate

The paper represents synthesis of the reconfigurable reversible fault-tolerant gate in the basis of generalized Fredkin gates. The gate is designed for an FPGA (Field Programmable Gate Array). Additionally, a genetic algorithm was used to optimize the characteristics of the circuit such as number of gates, quantum cost, delay, number of auxiliary inputs (garbage outputs). The model of the gate was created and verified in Active-HDL environment. Consequently, comparative analysis showed that the proposed design is fault-tolerant and it has more efficient quantum cost, gate count, and garbage outputs lines in contrast to the results of other authors.