8G Physical Coding Sub-layer Design Based on PCI Express 3.0 Protocol under 40nm Process

The PCI Express bus is a widely used high-speed serial bus standard. The PCS layer, as a sub-layer of the physical layer of the PCIe three-layer architecture, has an important status. A PCS layer circuit is designed based on the PCIe 3.0 protocol, which mainly includes data width adjustment circuit, data alignment circuit, elastic buffer and codec circuit. SMIC 40nm CMOS process is used to synthesize the circuit. Under the conditions of 500MHz clock, ss process angle and 125 °C temperature, the area is 69165um², and dynamic power consumption is 9.81mW. Tape tests show that the PCS layer circuit can be combined with the 8Gbps PMA layer to form a discrete physical layer chip, which supports 8GT/s transmission.