FPGA implementation of fixed-point arithmetic voltage mode controller for the Buck converter

A digital implementation of the voltage mode control for buck converters was designed and demonstrated on an FPGA development board. The digital control uses a fixed-point structure that increases the control accuracy without increasing the number of arithmetic operations. A soft-start function was included to minimize the output voltage overshoot at startup; an over-current protection function was also integrated in the experimental setup. The buck converter was designed to supply 3. 3V from an input voltage ranging from SV to 16V. Measurements results presented in the paper validate the design: 61mV maximum overshoot on startup; load transients of 164mV overshoot and 145. 5mV undershoot for a load jump from 150mA to 1. 1A, line transient of 236mV overshoot and 21SmV undershoot for 4V line jump and 44mV maximum output voltage ripple. The control loop stability margins were also assessed through measurements: they shown a minimum phase margin of 38.5° and a minimum gain margin of 11dB for a 16V input voltage and a 1. S4A load current.