Area Optimized FPGA Implementation of Slant Range Calculation Using Haversine Formula

In this study, the implementation of slant range calculation between two points on Xilinx Zynq series FPGA is shown. Although the calculation does not include very dense signal processing (DSP) blocks, it utilizes 28% memory (LUT) and 14% DSP blocks. With the time-division multiplexing (TDM) technique, more than one process was run on the same hardware blocks (resource sharing). Mathematical calculations were performed sequentially on the same hardware. In this way, the use of LUT was reduced to 18% and the use of DSP block was reduced to 5%. A reduction of nearly 40% has been achieved in the use of resources. The latency increase due to the ability of FPGAs to reach very high speeds does not prevent the calculation to be realtime. Truncation and rounding errors caused by fixed-point operations were kept below 1%.