Hardware Friendly Interweaved Prediction for Affine Motion Compensation

In the emerging next-generation video coding standard AVS3, interweaved prediction was proposed to further improve affine motion compensation (AMC). With interweaved prediction, a coding block with AMC mode is divided into subblocks with two different dividing patterns to generate two auxiliary predictions, and the final prediction is calculated as a weighted-sum of the two auxiliary predictions. Although interweaved prediction can provide a significant coding gain, it is not very friendly to the hardware design. In this paper, we present a hardware friendly interweaved prediction method, in which the off-chip memory bandwidth is reduced by limiting the reference sample number per pixel and the on-chip cache bandwidth is decreased by sharing reference samples between subblocks in pattern0 and pattern1 of interweaved prediction. Simulation results show that the proposed methods can achieve 0.47% BD-rate saving on average with the Random Access (RA) configurations while reducing 52.3% off-chip memory bandwidth and 62% on-chip memory bandwidth.