High Throughput Multiple Device Chain Diagnosis Methodology for Clock and Control Line Defects

Accuracy and throughput are the most important considerations for any scan-based diagnosis methods. When chain test fails on an Integrated Circuit (IC), massive failures must be logged to perform software-based chain diagnosis. Moreover, failing chain tests indicate presence of defects not just on the scan path but also on global signals such as clocks and control signals. For a successful volume diagnosis of chain failures, a methodology that can work with minimal failure logging and yet accurately identifies the defect locations with high throughput is desirable. In this paper, we propose a production proven scan chain diagnosis methodology based on multiple device diagnosis (MDD) that makes uses of a Design for Diagnosis (DFD) technique and accurately identifies clock and control signal defects in addition to defects in scan-paths. Accuracy results of the proposed methodology is proven through Physical Failure Analysis (PFA) on silicon, and the run time of the proposed algorithm achieved up to 19X speed-up over the incumbent approach.