Analysis of BTI Induced Input Buffer Aging Based on 32nm CMOS Process

This paper makes a breakthrough to accurately estimate and comprehensively analyze the transmission delay of input buffer caused by BTI aging via establishing aging model and comparing with standard logic unit. It presents the BTI aging for traditional input buffer within 10 years, designed in 32nm CMOS technology, and simulated with LTSPICE software. The use of Schmitt flip-flops as input buffers enables the circuit to increase noise tolerance and drive capability. The simulation results show that when the power supply voltage is 0.8V-1.1V, the transmission delay of input buffer will increase by 60% after 10 years under the influence of BTI aging, compared with 31% delay increment of CMOS 11-cascaded inverters under the same technology. In order to improve the reliability, the proposed technique named ICMT is introduced, which contributes to reducing 34% propagation delay for the input buffer.