Mitigation of Mutual Pulling in Two Phase-locked Loops

In this study, we analyzed the output phase of two mutually coupled phase-locked loops (PLLs) based on the numerical calculation of nonlinear equations. According to the results, when the two PLLs were completely synchronized, the circuits became unstable owing to mutual coupling in certain timing conditions. When the frequencies of PLLs were slightly different, the behavior of phase error depended on the frequency difference. The test circuit was fabricated through a 0.18 μm CMOS process, and the measured results were compared with the theoretical results. We confirmed the mitigation of mutual pulling in synchronous PLLs by adjusting the timing between the PLLs and observed two different modes of the phase error generation under the quasi-synchronous condition in the PLLs.