Development of planarizing spin-on carbon material for high-temperature processes

For the last several advanced semiconductor nodes, as the industry moves towards 7- and 5-nm processes, the requirements for patterning and image transfer have increased dramatically. Multilayer material stacks are needed to pattern complex high-resolution structures. For carbon films, one key point is the tradeoff between planarization and high-temperature stability requirements used in patterning and post-patterning process integration. On one side, the need for thermally stable carbon materials is steadily increasing, for better pattern transfer fidelity (less line wiggling), chemical vapor deposition (CVD) compatibility where a plasma-enhanced CVD (PECVD) inorganic hardmask is deposited on top, and for the use as mandrels for pattern multiplication. On the other hand, due to the increased complexity of chip designs, gap filling and planarization of the underlying topography is also strongly desired. In addition, wet chemical resistance and the capability to be polished by chemical mechanical planarization (CMP) processes are often necessary. Design of a spin-on carbon (SOC) film to meet all the desired, but sometimes conflicting, properties using organic polymers with good solubility in fab-approved solvent systems requires innovative chemical design and rigorous experiment and tuning processes. Brewer Science's advanced material development is bringing forth low-shrinkage, high-temperature-stable SOCs with spin-bowl/drain compatibility for advanced node manufacturing and integration. The materials presented in this paper are stable up to 500-550°C with no weight loss, soluble in solvents commonly used in semiconductor industry, can fill <; 10 nm narrow gaps, and have excellent planarization properties over a long distance. The coated film has very low thickness shrinkage during the bake conditions on the track and is stable through the subsequent high temperature PECVD process. The resulting dense carbon film provides extremely good planarization both locally and globally across the wafer. It demonstrated great chemical resistance to SC 1 conditions and can be CMP polished using commercially available slurries, if needed. During etch transfer, it showed very little after-develop inspection (ADI) and after-etch inspection (AEI) bias and maintained excellent line-width resolution through various critical dimensions. Moreover, this material's good solubility allows it to be formulated with high solid content for >2 μm thickness, which has showed early promising results in filling some very-high-aspect-ratio gaps in certain memory applications.