A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication

Nowadays, digital circuits are implemented in the Ultra Deep-Sub-Micron (UDSM) MOS technology. In UDSM-MOS technology, communication between subsystems may require several clock cycles, bringing about the communication of the two senses, an increasing penalty in latency and power. The QDI (Quasi Delay Insensitive) asynchronous circuits class is a design alternative in UDSM-MOS technology because this class does not use a clock signal, so it eliminates the problems related to the clock signal and is highly robust to PVT (process, supply voltage, and temperature) variations, which is pertinent to UDSM-MOS technology, due to its greater variability. Usually, the QDI class operates on the four-phase protocol, but this incurs a cost in communication between subsystems. In this paper, we propose a new asynchronous QDI pipeline architecture. Unlike other proposals, this architecture performs the communication with the environment is carried out using the QDI LEDR (Level-Encoded Dual-Rail) protocol, which is two-phase, therefore allows in communication a reduction in latency and power when compared to the QDI protocol of four phases. Through a case study, we show the efficiency of the new QDI pipeline.