Design and Simulation of Power efficient SRAM

Portable or handheld devices are growing at a fast pace nowadays and that is motivating designers to go for advanced low power circuit designs. The challenge is to reduce the existing topologies keeping the performance unhindered. Technology advances have always been accompanied by rise in the density of memory design. Power efficient memory designs are actively being used in biomedical sensors and space applications. The various designs in Static Random Access Memory (SRAM) circuit such as power dissipation, read and write cycle delays and signal-to-noise margin are modified by change in transistor sizing. In the present work, variation of width in a fixed technology length, also called as the aspect ratio in case of non-uniform lengths is chosen such that it best suits the requirements. The effect of change in transistor size on power dissipation of the SRAM cell circuit is discussed. The 6T SRAM cell configuration is one of the most widely used because of its speed and lesser sensitivity to noise and soft errors. The results show that the implemented circuit has lower power dissipation and comparable delays to the existing circuits. The proposed circuit has a power dissipation of 53pW and a delay of 77ps @Vdd=1.8V on 250nm technology length.