Features of Snapback in Compact Memory Devices For High Performance Integrated Circuits

This paper provides physical insight of ZRAM (Zero Capacitor RAM) based on space charge limited (SCL) model. 2-D NMOS device is characterised and it's operation area is explored by technology computer aided design (TCAD). In particular, with proper selection of the current ramp at the drain, carrier electrostatics is examined. It analyses the snapback phenomenon in capacitor-less memory under high current application at drain of gate grounded NMOS devices. Physics of current crowding phenomenon under ambipolar injection from the drain is analysed. The work evaluates the electrostatics of the problem in terms of surface and bulk to understand mechanisms of current flow. An analytical model is established to show lesser impact of surface bipolar turn-on under snapback and its larger impact in the bulk impacted by applying bias to the gate.