A Hetero-Dielectric Double-Gate Junctionless FET with Spacer for Improved Device Performances

In this paper, we lay out a simulation study of DC parameters for a hetero-dielectric junctionless field transistor along with the best possible combination of high-k/low-k spacer dielectric on both ends of the gate oxides of the device. Various parameters, such as ON-current, subthreshold leakage current and current switching ratio are analyzed and compared with single-material gate (i.e. conventional) DG-JLFET. A significant improvement in the current switching ratio is observed for the presented device when the length ratio of two gate oxides is kept at an optimum value with high-k and low-k spacer on source and drain end, respectively. It is mainly attributed due to the fact that different spacer and gate dielectric introduced at both the ends alters the fringing electric field along the channel, mainly at channel-drain interface, and eventually reduces the OFF-state current by at least 100 fold as compared to that of SMG-JLFET.