Simulation of Low Power DVCC Based LNA for Wireless Receiver

The use of a low-voltage PMOS bulk-driven cascade current mirror (P MOS BDCCM) to realize LNA using CMOS differential voltage current conveyor (DVCC) based on low power and free from trans-conductance variation is presented in this research paper. Just one current mirror is used in this circuit, which uses four DVCCs as active elements and two capacitors and five resistors as passive elements. The use of this active component simplifies and improves the deployment process. The circuit is consuming Low Power of 1.24mW with the Voltage gain of 2.21 dB for the input voltage of 1V and seems to operate in 1- 10 GHz. The circuit's functionality is checked using Tanner simulator version 16 for a 35µm CMOS process model, and the transfer function is realized using MATLAB R2017a, yielding a variety of simulation results. To show the outcomes, simulation results are included.