An SOI n-p-n Double Gate TFET for Low Power Applications

This article proposes a tunnel field effect transistor (TFET) based on n-p-n silicon body with double gates, one each over the two p-n junctions. The p-type source region is elevated as compared to the two n-type drain regions in order to create sufficient length for gate placement, and cover the junction. Electrical parameters have been systematically investigated through calibrated TCAD (technology computer aided design) simulations with objectives to reduce the ambipolar currents, and increase the ratio of on and off currents. Gate-on-drain length is an important parameter to control ambipolarity in the device, similar to gate-drain underlap length in conventional TFETs. Sub-60 mV/dec subthreshold swings, and drain current usually in order of tens of μA/μm have been observed. Gate workfunction engineering further shows the tuning of threshold voltage, and other electrical parameters.