Performance Analysis of FinFET based inverter at 7nm Technology Node Using TCAD Simulation

In this work, a layout-based FinFET design approach has been presented at 7nm technology node. Using Technology CAD (TACD) physic based tool, the electrical performances have been investigated for both n and p-channel FET. A mixed-mode integrated simulation environment has been implemented to realize the CMOS inverter for circuit applications. The signal propagation across the designed inverter has been investigated. The improvement in maximum power (P
_max
) performance and switching energy behavior can be observed with variation in drain voltage and fin height.