A Novel Junction Less Dual Gate Tunnel FET with SiGe Pocket for Low Power Applications

A novel junction-less dual gate tunnel FET device with P+ Si
_1-x
Ge
_x
pocket near the source end is introduced in this paper. The device exhibits sharp subthreshold slope of 63.5mV/dec, very high I
_ON
/I
_OFF
ratio of 10
¹¹
and low drain induced barrier lowering (DIBL) of 22.2mV/V. The junction less behaviour and high-k gate oxide/high work function gate contact boosts the ON current in the device. The double gate enhances the control of the gate on channel conduction and improves the drain current. The P+ pocket near the source end having narrow band gap material Si
_1-x
Ge
_x
drastically reduces the tunnelling length and increases the I
_ON
/I
_OFF
ratio. The device is designed and simulated on Visual TCAD (Cogenda) device simulator for 18nm gate length. The device is simulated for various pocket materials and gate contact/oxide combinations to propose the present one. It has been tested for various gate length and SiGe mole fraction variations. It is also found to be efficiently operational over a wide range of temperature from 200K to 400K.