Validation of Input/Output characteristics of Symmetrical Double Source TFET device

Double Source SOI Tunnel FET (DSS- TFET) of both n and p-type has been proposed and influence of various parameters on the efficiency of the device have been analyzed rigorously and optimized using Silvaco-Atlas. The proposed DSS-TFET has been designed in such a way that by suppressing the ambipolar current, complementary performance can be achieved. The DSS-TFET has almost equivalent SS for different channel lengths. Hence, during circuit designing, 13nm n- type TFET and 5nm p-type TFET can be utilized which results in chip area reduction. As SOI architecture is used, ambipolar conduction has been improved, results in higher ION/IOFF ratio of. value 10¹³ and 10¹² for both n and p type respectively.