Single-Phase, Single-Loop PLL-Based BPSK, QPSK, 8-PSK Demodulators

A general single-phase/single-loop PLL-based m-PSK demodulator is described. The demodulator employs a rising-edge RS flip-flop as a phase detector because of its linear / over a 0-2π phase difference. This flip-flop characteristic helps simplify the phase controller design and make it truly modular. The phase controller basically explores a sub-ranging/re-scaling technique similar found in a typical ADC converter. The proposed principle has been implemented with discrete components around 74HCT4046 for demodulating BPSK, QPSK and 8-PSK signals. The modulator prototypes operate under a single supply of 5V achieving a maximum data rate of 40kbps at a carrier frequency around 120-kHz. Experimental comparison with a widely-used Costas-Loop BPSK demodulator suggests that the proposed structure offers a competitive performance.