A Linearized Charge Pump for Power and Phase Noise Efficient Fractional-N PLL Design

This paper presents the design and implementation of Charge Pump (CP) circuit to improve the mismatch in currents with good linearization in Low Voltage Fractional-N PLL suitable for RF applications. In this work a linearized Charge Pump circuit having mismatch in current of less than 2 % where variation in current be of ± 1.2%, for the output voltage to be 0.12 to 0.34 V with in a 0.45 V, and 0.13 to 1.63 V with in a 1.8 V supply voltage. A good linearization between Charge pump circuit with Digital Delta Sigma Modulator (DDSM). The circuit is implemented in CMOS process technology using cadence, Virtuoso tool by Generic Process Design Kit (GPDK 45nm). The proposed Charge Pump circuit uses in the design of Fractional-N Charge Pump PLL as a frequency synthesizer for any portable wireless applications.