A Lightweight Configurable XOR RO-PUF Design Based on Xilinx FPGA

Lightweight electronic devices are emerging as a promising electronic equipment. Physical unclonable function (PUF), a kind of authentication circuit in lightweight electronic chip, is very useful component in secure system design. The reliability and uniqueness of PUF is limited by the complexity of its circuit. Herein, a reconfigurable XOR gate PUF based on configurable delay line is demonstrated to obtain lightweight chip certification circuit. Owing to the same number of configurable logic blocks (CLBs) in the FPGA implementation, the PUF can generate more challenge response pair (CRP) well. The PUF exhibits a much better uniqueness and reliability than previous other types of PUF designs when this design is implemented in multiple Xilinx Virtex-6 FPGAs. Moreover, this PUF consumes less than 0.05% of hardware resources to generate a 1-bit response than other configurable PUFs implemented in FPGA.