DFT Models of Ferroelectric Hafnium-Zirconium Oxide Stacks With and Without Dielectric Interlayers

Endurance is a key material performance metric for device and memory applications and is diminished due to defect formation. Defects alter material properties and relative phase stability, adversely affecting the reliability of devices. Ferroelectric field-effect transistors (FEFETs) have metal-insulator-semiconductor (MIS where I=ferroelectric) gate stacks which typically show unsatisfactory endurance of about 10 5 cycles, [1] while metal-insulator-metal (MIM where I=ferroelectric) capacitors can demonstrate endurance up to 10 12 . Adding a linear dielectric (DE) interlayer at the FE-semiconductor interface may enhance the endurance by suppressing defect formation due to oxygen vacancies, [1] but the electrostatic role of the DE interlayer has not been clearly examined yet. Here, DFT is employed to develop an atomic and electronic level understanding of the behavior of atoms in MIM and MIS stack models with and without DE interlayers due to polarization switching.