Cool-CMOS Technology for Next Generation High Performance Computing

Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. The relentless scaling of integrated circuit (IC) technology has enabled ever faster, smaller, and lower energy electronics in last 60 years. However, as the CMOS transistor switching energy and latency get limited by the tyranny of thermionic switching, the pace of improvement will slow down. A decadelong research on post-CMOS devices to replace CMOS and improve its energy-latency figure-of-merit by >100X has not conclusively identified any killer device technology. In this context, deeply scaled cryogenic-CMOS or Cool-CMOS harnesses operating temperature as the primary knob to achieve the ultimate energy-delay performance limit. Beyond steeper slope and improved channel transport, critical cryogenic boosters like improved device-reliability, enhanced thermal dissipation capability and higher conductivity of scaled metal lines enable high activity ultra-fast CMOS-based circuits, where the candidate applications can span from high performance servers in data centers to the control electronics for quantum computing. In this talk, we will discuss about each of these performance boosters along with the compact modeling approaches for deeply-scaled Cool-CMOS transistors. The talk will conclude by outlining the design technology co-optimization critical for attaining Cool-CMOS based logic and memory for ultra-high performance computing.