A Twin Bit AND-Type Multiple-Time-Programming Memory Cell by Nano-scaled High-κ Metal Gate Process

A multiple-time programmable (MTP) twin-bit memory cell with metal floating gate coupled by n-well program gate is proposed and implemented by standard CMOS logic processes. Equipped with high programming gate coupling ratio controlled well by overlap area design, a twin bit cell with a pair of symmetric floating gates is successfully demonstrated. In addition, this memory also shows good endurance and low disturbance during the P/E cycling tests.