A precise debugging method and defect diagnosis with mass big-data analysis in the designed high-dense array for rapid yield improvement in a logic platform

A novel high-density test array is designed to capture device outliers and defects among the transistors at the parts per million (ppm) level for rapid yield improvement. The array design can achieve a very high design density (>1 million devices per die) while protecting the actual product environment. An on-chip controller enables a breakthrough test speed of up to 10,000 items per second per channel. With this test-chip and a custom-built analytics platform, a variety of device outliers can be captured to support process development and yield ramp-up in a short time. In this paper, we show one real example where the small pin-hole, existing in the contact material, cannot be monitored by the traditional contact resistance measurement. However, it can be extracted successfully by our designed high-dense array. With the corresponding process improvement and this developed debugging method, the yield can be easily evaluated and ramped up quickly in a short time for logic process development.