Strategy for Simulation of Analog Circuits with GCSOI MOSFET using BSIM SOI model

This work presents a simulation strategy to simulate Graded-Channel SOI MOSFET electrical characteristics using BSIM SOI SPICE model. The use of uniformly doped transistor model is possible by adjusting low field mobility, degradation mobility factors and parameters related to channel length modulation and DIBL effects. A good agreement with experimental data was achieved at device level. The simulation strategy is validated through the simulation of common-source current mirrors using adjusted SPICE model parameters, presenting the same trends of experimental results available in the literature.