3D-Split SRAM: Enabling Generational Gains in Advanced CMOS

3D integration technologies are becoming increasingly viable to mitigate the limitations and slowdown in traditional 2D transistor scaling. 3D-Split SRAMs, realized by splitting the bitlines (BL) and/or wordlines (WL) across two or more 3D-arranged tiers, promise improved power/performance due to reduced RC parasitics. However, their feasibility and efficacy depend on the pitch and RC parasitics of the inter-tier BEOL connections (3D-BEOL). In this work, we analyze the impact of 3D-BEOL on the 3D-Split SRAM gains, in a face-to-face (F2F) hybrid wafer bonding 3D integration technology. Two separate approaches for reducing 3D-BEOL parasitics viz (1) M
Z
-Supervia, & (2) M
Z
-less 3D-BEOL are proposed. Measurements from 64 Kb 12 nm FinFET SRAM prototype, reconfigured to capture the BL-split and the WL-split 3D SRAM effects, show up to 107 mV lower V
min
as well as $\sim$15% better access-time, equivalent to the performance gains from one technology node dimensional scaling.