Annealing processors [1] –[4] based on the Ising model and quantum or simulated annealing mechanism recently have gained significant attention due to the unique capabilities of solving problems based on the convergence behavior in the stochastic spin interactions. Spin is a neuron-like binary (i.e. -1 or +1) unit of annealing processors, and a network of such spins solves combinatorial optimization problems by minimizing its Hamiltonian (or energy of the system) to the ground state. Although prior works [1] –[3] have demonstrated the annealing processors’ capability to solve problems that are ill-suited to classical computers, their applications are limited due to simple and fixed spin networks, such as lattice, Chimera [1], and King’s graph –[3]. As shown in Fig. 1 (top-left), vertices (i.e. spins) in simple graphs interact with neighbors via local interconnects, and the number of neighbors is typically limited to 4-to-8. Fig. 1 (top-center) shows a recent work [4] implementing a complete graph with fully-connected spins based on the near-memory computing architecture. However, it requires a significant energy overhead and results in scalability challenges due to the excessive hardware complexity. The number of interconnects increases quadratically in proportion to the number of spins.
Abstract:
Annealing processors [1] -[4] based on the Ising model and quantum or simulated annealing mechanism recently have gained significant attention due to the unique capabilit...Show MoreMetadata
Abstract:
Annealing processors [1] -[4] based on the Ising model and quantum or simulated annealing mechanism recently have gained significant attention due to the unique capabilities of solving problems based on the convergence behavior in the stochastic spin interactions. Spin is a neuron-like binary (i.e. -1 or +1) unit of annealing processors, and a network of such spins solves combinatorial optimization problems by minimizing its Hamiltonian (or energy of the system) to the ground state. Although prior works [1] -[3] have demonstrated the annealing processors' capability to solve problems that are ill-suited to classical computers, their applications are limited due to simple and fixed spin networks, such as lattice, Chimera [1], and King's graph -[3]. As shown in Fig. 1 (top-left), vertices (i.e. spins) in simple graphs interact with neighbors via local interconnects, and the number of neighbors is typically limited to 4-to-8. Fig. 1 (top-center) shows a recent work [4] implementing a complete graph with fully-connected spins based on the near-memory computing architecture. However, it requires a significant energy overhead and results in scalability challenges due to the excessive hardware complexity. The number of interconnects increases quadratically in proportion to the number of spins.
Published in: 2021 IEEE Custom Integrated Circuits Conference (CICC)
Date of Conference: 25-30 April 2021
Date Added to IEEE Xplore: 17 May 2021
ISBN Information: