Self-Heating Effects from Transistors to Gates

With the introduction of FinFET transistors, the Self-Heating Effect (SHE) became a major reliability challenge. In this work, we present an automated SHE estimation method integrated within a circuit reliability framework. It allows designers to study SHE in analogue and digital circuits. For accurate analysis, we employ electrically and thermally calibrated 14nm FinFET transistor models. To demonstrate the capabilities of our framework, we study SHE in standard cells and report a considerable dependence on the cell topology. We show how SHE can induce 15% delay increase in AND3 logic gate, highlighting the importance of taking SHE into account. Otherwise, reliability cannot be sustained during the circuit's operation.