A Reconfigurable In-SRAM Computing Architecture for DCNN Applications

A methodology for Artificial Intelligence (AI) edge Deep Learning Neural Network (DNN) hardware design to increase the flexibility of each layer is emergent required. In order to support different DNN layers, a reconfigurable Universal Computation Element (UCE_R) is proposed. The UCE_R has its own controller and several UCE_Rs can be integrated to form a Reconfigurable UDNN (UDNN_R) engine for use in different kinds of AI edge applications. The design of UCE_R is implemented by using TSMC CMOS 28 um process. An UDNN_R is integrated for a Mobile_Net application.